1. Field of the Invention
The present invention relates to a semiconductor memory device such as a pseudo static random access (PSRAM) device requiring a refresh operation and its driving method.
2. Description of the Related Art
As random access memory (RAM) devices, there are static random access memory (SRAM) devices and dynamic random access memory (DRAM) devices.
Firstly, the SRAM devices have an advantage that the SRAM devices can be operated at a higher speed than the DRAM devices.
Secondly, the SRAM devices have an advantage that the SRAM devices can be accessed, i.e., read from or written to by a simpler control than that of the DRAM devices. That is, in the SRAM devices, when an address signal is simply supplied thereto, an access operation such as a read operation or a write operation is carried out. On the other hand, in the DRAM devices, when a row address signal associated with a row address strobe (RAS) signal and a column address signal associated with a column address strobe (CAS) signal are supplied thereto, an access operation such as a read operation or a write operation is carried out.
Thirdly, the SRAM devices have an advantage in that the power consumption can be smaller than that of the DRAM devices. That is, the DRAM devices require a refresh operation for holding the memory content thereof even in a standby mode, while such a refresh operation is unnecessary in the SRAM devices.
However, the DRAM devices have an advantage in that the DRAM devices have a smaller size than that of the SRAM devices. That is, in the SRAM devices, one cell is generally constructed by six MOS transistors, while in the DRAM devices, one cell is generally constructed by one MOS transistor and one capacitor.
Therefore, the SRAM devices are suitable for use in mobile stations in terms of the higher speed characteristics, the simpler controllability and the decreased power consumption, in spite of the smaller memory capacity.
However, recently, as mobile stations can communicate with E-mail and access Web sites, memories incorporated into the mobile stations have been required to have a larger memory capacity.
In order to satisfy the demand for memories incorporated into the mobile stations, pseudo SRAM devices having the above-mentioned advantages of the SEAM devices and the above-mentioned advantage of the DRAM devices have been focussed on. That is, in the pseudo SRAM devices, when an address signal without a RAS signal and a CAS signal is supplied thereto and is fetched by a chip enable (CE) signal, an access operation such as a read operation or a write operation is carried out in synchronization with an external clock signal at a higher speed than the DRAM devices.
The pseudo SRAM devices, however, still require a refresh operation for holding the memory contents in a standby mode, which is different from the conventional SRAM devices. That is, the pseudo SRAM devices have a similar cell configuration to the DRAM devices and an SRAM interface operated in synchronization with an external clock signal. A first typical pseudo SRAM device is a synchronous mobile SRAM (MSRAM) device whose cell is constructed by one MOS transistor and one capacitor (see: JP-2002-074944-A), and a second typical pseudo SRAM device is a dual port SRAM (2T-PSRAM) device whose cell is constructed by two MOS transistors and one capacitor (see: FIG. 2 of JP-2001-210074-A).
In the above-mentioned pseudo SEAM devices, an all-time refresh operation is carried out in an active mode by raising the voltages at refresh word lines triggered by an all-time refresh pulse signal in synchronization with an external clock signal, while a forced refresh operation is carried out in a special mode by raising the voltages at the refresh word lines triggered by an internally-generated forced refresh pulse signal. In this case, the all-time refresh pulse signal and the forced refresh pulse signal both have much larger periods than that of the external clock signal.
As illustrated in FIGS. 1A, 1B and 1C, in the active mode of the synchronous MSRAM devices, a read/write pulse signal RWP for normal word lines alternates with the refresh pulse signal REFP, thus avoiding the destruction of cell information. Note that, if the read/write pulse signal RWP and the refresh pulse signal REFP rise simultaneously, a multi-selection occurs to destroy cell information. Also, if a refresh pulse signal REFP rises while a restoring operation is being carried out after an all-time refresh pulse signal rises, cell information also would be destroyed.
On the other hand, as illustrated in FIGS. 2A, 2B and 2C, in the active mode of the 2T-PSRAM, since use is made of a two-port configuration, a read/write operation using a read/write pulse signal RWP for the normal word lines is carried out for one port, while a refresh operation using a refresh pulse signal REFP for the refresh word lines is carried out for the other port, thus decreasing the control time.
Note that, in the active mode of the 2T-PSRAM devices, a small difference between the voltage at a first one of one pair of bit lines and a reference voltage is sensed by the read/write pulse signal RWP to carry out a read operation, while a refresh operation is performed by the refresh pulse signal REFP upon a second one of the pair of bit lines. Therefore, if the timing of the refresh operation is shifted or advanced from its optimum timing, the rapid change of the voltage at the second bit line affects the sense operation of the first bit line due to the noise by crosstalk, thus destroying cell information.
Four special modes other than the active mode will now be explained.
(1) Sleep Mode (ZZ Mode)                A sleep mode is defined by a state where no external clock signal CLK is supplied to the device.        
(2) Stop Clock Mode (Chip Selection Mode)                A stop clock mode is defined by a state where an external clock signal CLK supplied to the device is temporarily stopped. This is also called a chip selection (CCS) mode.        
(3) Clock Non-selection Mode                A clock non-selection mode is defined by a state where an external clock signal CLK is supplied to the device but the external clock signal CLK is not selected by a clock enable signal CKE within the device.        
(4) Long Cycle Mode                A long cycle mode is defined by a state where the frequency of an external clock signal supplied to the device is lower than a predetermined value.        
In the sleep mode, the stop clock mode or the clock non-selection mode, use is never made of the external clock signal CLK. In the long cycle mode, incomplete use is made of the external clock signal CLK.
In a special mode, a forced refresh pulse signal is generated as an internal clock signal within the device to carry out a refresh operation using the refresh word lines.
When the control is transferred from one of the special modes to an active mode, an access operation such as a read operation or a write operation is restarted by using a read/write pulse signal generated in synchronization with the external clock signal CLK.
However, as illustrated in FIGS. 3A, 3B, 3C, 3D and 3E, since a forced refresh pulse signal (internal click signal) REFB is not in synchronization with an external clock signal CLK which is substantially a signal CLK′ within the device, a refresh pulse signal REFP for the refresh word lines derived from the forced refresh pulse signal REFB is not in synchronization with a read/write pulse signal RWP for the normal word lines derived from the signal CLK′. As a result, in the synchronous MSRAM devices, when the read/write pulse signal RWP is superposed onto the refresh pulse signal REFP immediately after transition from a special mode to an active mode, a word line multi-selection would occur or a restore operation would be intercepted. On the other hand, in the 2T-PSRAM devices, when the read/write pulse signal RWP is shifted from the refresh pulse signal REFP immediately after transition from a special mode to an active mode, a sense operation would be incomplete.
Thus, it was difficult for the prior art pseudo SRAM device to smoothly transfer a special mode to an active mode.